Heretofore, in receiving serial transmission data in the high-speed serial transmission of a digital signal (data), a scheme has been generally employed wherein the serial transmission data is sampled by using a sampling clock signal which has a frequency equal to a bit rate of the serial transmission data and which is synchronized with the serial transmission data.
In accordance with such a simple sampling scheme, however, when sampling the serial transmission data by using the sampling clock signal, the phase of the serial transmission data is shifted relative to that of the sampling clock signal due to a deviation of signal delay in a transmission line (this phenomenon is called as “skew”), or the waveform of the serial transmission data itself is degraded, so that symbol values cannot be perfectly detected in some cases.
In the design of a reception circuit which receives the digital signal serially transmitted at high speed, therefore, a circuit technique has become important which can stably detect the symbol values even in the case where such a degraded serial transmission data has been received.
In recent years, an oversampling scheme, which detects the symbol values at a number of sampling points larger than a number of bits of the serial transmission data, has been employed as a sampling scheme which is effective for stably detecting the symbol values even in the case of receiving the serial transmission data having the waveform degraded in the transmission line.
For example, U.S. Pat. No. 5,802,103 discloses an example of a fully duplexed transmission system wherein reception data is detected by using the oversampling scheme in high-speed serial transmission. As disclosed in the document, in the case of using a triple oversampling scheme, a phase shift of at most ±30% can be allowed with respect to a symbol period (which corresponds to the inverse number of a number which is obtained by multiplying a clock frequency by a number of bits in one data block) even when the phase of serial transmission data is shifted relative to the phase of the sampling clock signals.
FIG. 1 is a block diagram showing an example of a prior-art reception circuit which employs an oversampling scheme. In this example, a number of bits in one data block is 8 bits, and oversampling is performed at triple a bit rate of the serial transmission data.
As shown in FIG. 1, the reception circuit includes a PLL or DLL circuit 210 which generates from an input clock signal multiphase clock signals which afford a sampling rate at triple a bit rate of the serial transmission data, a sampling register 220 which oversamples the serial transmission data by using the multiphase clock signals, and a logic-value determination circuit 230 which determines symbol values of 8 bits included in one data block on the basis of the result of the oversampling.
The serial transmission data of one block (8 bits) inputted to the sampling register 220 is oversampled at 24 sampling points, which are triple the number of symbol bits, and the oversampled data is outputted as parallel data of 24 bits.
The logic-value determination circuit 230 executes a probability computation by using the parallel data, thereby to find the transition points of the serial transmission data. Further, the logic-value determination circuit 230 executes re-sampling for selecting appropriate parallel data of 8 bits from among the 24-bit parallel data obtained by the oversampling, on the basis of the transition points, thereby to finally determine the symbol values of 8 bits.
FIG. 2 is a diagram for explaining operations of the reception circuit shown in FIG. 1, in terms of logic values. One data block of the serial transmission data inputted to the reception circuit is oversampled by the multiphase clock signals which have a frequency being triple the bit rate thereof, with the result that the sampled data is outputted as the 24-bit parallel data which reflects the logic values of the serial transmission data.
The probability computation is executed by using the parallel data, whereby the transition points 201-205 are determined. By way of example, when the same logic value is consecutive twice in the sampled parallel data, the existence of the transition point is determined. The symbol values of 8 bits are determined from among the 24-bit parallel data, on the basis of the transition points thus determined.
In accordance with the oversampling scheme, however, a number of sampling clocks and a number of sampling circuits increase, so that a substrate area and a consumption current, which are required in a semiconductor integrated circuit, increase. In the design of a semiconductor integrated circuit employing an oversampling scheme at triple, quadruple or higher, therefore, the problem is coped with by adopting advanced minuter semiconductor technology, but there has been a problem that a manufacturing cost rises.